The present invention relates to a semiconductor memory including a test circuit for detecting cell transistor leakage failure of a memory cell and a test method for the semiconductor memory.
A system LSI (large scale integrated circuit) mixedly includes semiconductor memories such as a DRAM (dynamic RAM) and an SRAM (static RAM), and the proportion of semiconductor memories in the chip area of a system LSI is increasing year by year.
Some of these semiconductor memories include a memory cell in which a transistor (hereinafter referred to as the access transistor) and a capacitor (hereinafter referred to as the memory cell capacitor) are connected to each other in series. In such a semiconductor memory, when there is failure in, for example, a PN junction formed between a node of the access transistor and a substrate, the level of a sub bit line may be lowered due to leakage caused in this defective memory cell. In this case, the potential of nodes of the other normal memory cells connected to the same sub bit line is lowered. In particular, in the case where data written in a memory cell capacitor of a normal memory cell is at H level, a potential difference caused between the source and the drain of the access transistor is increased. Therefore, the leakage caused in the access transistor is accelerated, and hence, it is apprehended that the data stored in the normal memory cell may be lost (which corresponds to the so-called disturbed state). Accordingly, it is necessary to screen such a defective memory cell through a test.
Some of conventional semiconductor memories can be subjected to a test for an operation margin under severe conditions such as a case where the potential of a sub bit line is lowered (see, for example, Japanese Laid-Open Patent Publication No. 8-195100). In this technique, the operation margin is tested with the potential of a sub bit line pair lowered in a semiconductor memory having a hierarchical structure including main bit line pairs and sub bit line pairs. Specifically, in a given block of memory cells of this semiconductor memory, one sub bit line pair is precharged and then placed in a floating state and main bit lines of a corresponding main bit line pair are short-circuited so as to lower the potential of the sub bit line pair, and under these conditions, the operation margin is checked. Through this test, a semiconductor memory having a sufficient margin for leakage can be selected.
This test is, however, performed on each block of the semiconductor memory, and hence, as the capacity of the semiconductor memory is increased and the number of blocks is increased, the time necessary for the test is increased, which disadvantageously increases the test cost. Furthermore, leakage of a memory cell itself cannot be detected in this test.